The ESD issue is an essential consideration in design and operation of integrated circuit devices. Inputs and outputs of the integrated circuits may be subject to undesirable ESD. Usually the fast, transient and high-voltage ESD would cause destructive damage of the integrated circuits, such as the dielectric breakdown of oxides. To overcome such a problem, various ESD protection circuits have been used at input or output terminals of the integrated circuits to provide a safe path for the ESD current to bypass. Once an ESD zaps, the ESD current is discharged through the ESD protection circuit, thus preventing the integrated circuit to be protected from damage.
Conventional ESD protection circuits are based on the lateral structure of NPN or PNP transistors or require additional trigger elements to speed up turning-on of the transistors. To minimize integrated-circuit layout area for an ESD protection circuit, it is desirable to integrate a parasitic trigger element with a transistor switch having a vertical structure. Furthermore for reasons of both positive and negative ESD protection, it is preferable to develop an ESD protection device with protective ability for both positive and negative ESD currents.